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| K6F1008V2C Family Document Title 128Kx8 bit Super Low Power and Low Voltage CMOS Static RAM CMOS SRAM Revision History Revision No. 0.0 0.1 History Initial Draft Revise - Changed Package Type : 48(36)-TBGA-6.00x7.00 to 32-TSOP1-0813.4F Finalize Draft Data November 27, 2001 December 13, 2001 Remark Preliminary Preliminary 1.0 June 12, 2002 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices. 1 Revision 1.0 June 2002 K6F1008V2C Family CMOS SRAM 128Kx8 bit Super Low Power and Low Voltage CMOS Static RAM FEATURES * * * * * * GENERAL DESCRIPTION The K6F1008V2C families are fabricated by SAMSUNGs advanced full CMOS process technology. The families support industrial temperature range and have various package types for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current. Process Technology: Full CMOS Organization: 128K x8 bit Power Supply Voltage: 3.0~3.6V Low Data Retention Voltage: 1.5V(Min) Three State Outputs Package Type: 32-TSOP1-0813.4F PRODUCT FAMILY Power Dissipation Product Family Operating Temperature Vcc Range Speed Standby (ISB1, Typ.) 0.5A2) Operating (ICC1, Max) 3mA PKG Type K6F1008V2C-F Industrial(-40~85C) 3.0~3.6V 551)/70ns 32-TSOP1-0813.4F 1. The parameter is measured with 30pF test load. 2. Typical values are measured at VCC=3.3V, TA=25C and not 100% tested. PIN DESCRIPTION A11 A9 A8 A13 WE CS2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 FUNCTIONAL BLOCK DIAGRAM Clk gen. Precharge circuit. 32-sTSOP Type1-Forward Row select Memory array 1024 rows 128x8 columns I/O1 I/O8 Data cont I/O Circuit Column select Data cont Name Function Name Function CS1 CS2 WE OE CS1, CS2 Chip Select Inputs OE WE A0~A16 Output Enable Input Write Enable Input Address Inputs I/O1~I/O8 Data Inputs/Outputs Vcc Vss NC Power Ground No Connection Control logic SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 1.0 June 2002 K6F1008V2C Family PRODUCT LIST Industrial Temperature Products(-40~85C) Part Name K6F1008V2C-YF55 K6F1008V2C-YF70 Function CMOS SRAM 32-sTSOP1-F, 55ns, 3.3V 32-sTSOP1-F, 70ns, 3.3V FUNCTIONAL DESCRIPTION CS1 H X1) L L L CS2 X 1) OE X 1) WE X 1) I/O High-Z High-Z High-Z Dout Din Mode Deselected Deselected Output Disabled Read Write Power Standby Standby Active Active Active L H H H X1) H L X 1) X1) H H L 1. X means dont care (Must be high or low states) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOUT VCC PD TSTG TA Ratings -0.2 to VCC+0.3V -0.2 to 4.0V 1.0 -65 to 150 -40 to 85 Unit V V W C C 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted within recommended operating condition. Exposure to absolute maximum rating conditions for extended period may affect reliability. 3 Revision 1.0 June 2002 K6F1008V2C Family RECOMMENDED DC OPERATING CONDITIONS1) Item Supply voltage Ground Input high voltage Input low voltage Note : 1. TA=-40 to 85C, otherwise specified 2. Overshoot: Vcc+2.0V in case of pulse width 20ns. 3. Undershoot: -2.0V in case of pulse width 20ns. 4. Overshoot and undershoot are sampled, not 100% tested. CMOS SRAM Symbol Vcc Vss VIH VIL Min 3.0 0 2.2 -0.3 3) Typ 3.3 0 - Max 3.6 0 Vcc+0.3 0.6 2) Unit V V V V CAPACITANCE1) (f=1MHz, TA=25C) Item Input capacitance Input/Output capacitance 1. Capacitance is sampled, not 100% tested Symbol CIN CIO Test Condition VIN=0V VIO=0V Min - Max 8 10 Unit pF pF DC AND OPERATING CHARACTERISTICS Item Input leakage current Output leakage current Average operating current Symbol ILI ILO ICC1 ICC2 Output low voltage Output high voltage Standby Current(CMOS) VOL VOH ISB1 VIN=Vss to Vcc CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc Cycle time=1s, 100%duty, IIO=0mA, CS10.2V, CS2Vcc-0.2V, VIN0.2V or VINVCC-0.2V Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL Test Conditions Min Typ 1 Max Unit -1 -1 2.4 0.5 1 1 3 35 0.4 5 2) A A mA mA V V A IOL=2.1mA IOH=-1.0mA CS1Vcc-0.2V, CS2Vcc-0.2V or CS20.2V, Other inputs=0~Vcc 1. Typical values are measured at VCC=3.3V, TA=25C and not 100% tested. 2. Super low power product=1A with special handling. 4 Revision 1.0 June 2002 K6F1008V2C Family AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Test Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load (See right): CL= 100pF+1TTL CL = 30pF+1TTL CMOS SRAM VTM3) R12) CL1) R22) 1. Including scope and jig capacitance 2. R1=3070, R2=3150 3. VTM =2.8V AC CHARACTERISTICS (Vcc=3.0~3.6V, Industrial product:TA=-40 to 85C) Speed Bins Parameter List Symbol Min Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Read Chip Select to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z 1. The parameter is measured with 30pF test load. 55ns 1) 70ns Max 55 55 25 20 20 20 Min 70 10 5 0 0 10 70 60 0 60 50 0 0 30 0 5 Max 70 70 35 25 25 20 - Units tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW 55 10 5 0 0 10 55 45 0 45 40 0 0 25 0 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DATA RETENTION CHARACTERISTICS Item Vcc for data retention Data retention current Data retention set-up time Recovery time Symbol VDR IDR tSDR tRDR CS1Vcc-0.2V 1) Test Condition Min 1.5 0 tRC Typ - Max 3.6 1.0 - Unit V A ns Vcc=1.5V, CS1Vcc-0.2V1) See data retention waveform 1. CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) or CS20.2V(CS2 controlled) 5 Revision 1.0 June 2002 K6F1008V2C Family TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH) tRC Address tOH Data Out Previous Data Valid tAA CMOS SRAM Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO1 CS1 tHZ(1,2) CS2 tCO2 tOE tOH OE tOLZ tLZ Data Valid tOHZ Data out NOTES (READ CYCLE) High-Z 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 1.0 June 2002 K6F1008V2C Family TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) CMOS SRAM tWC Address tCW(2) CS1 tAW CS2 tCW(2) tWP(1) WE tAS(3) Data in tWHZ Data out Data Undefined tDW Data Valid tOW tDH tWR(4) TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled) tWC Address tAS(3) CS1 tAW CS2 tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4) Data out High-Z High-Z 7 Revision 1.0 June 2002 K6F1008V2C Family TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled) tWC Address tAS(3) CS1 tAW CS2 tCW(2) tWP(1) tDW Data in Data Valid tDH tCW(2) tWR(4) CMOS SRAM WE Data out NOTES (WRITE CYCLE) High-Z High-Z 1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 going low, CS2 going high and WE going low : A write ends at the earliest transition among CS1 going high, CS2 going low and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS1 going low or from CS2 going high to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR1 is applied in case a write ends with CS1 or WE going high and tWR2 is applied in case a write ends with CS2 going low. DATA RETENTION WAVE FORM CS1 controlled VCC 3.0V tSDR Data Retention Mode tRDR 2.2V VDR CS1VCC - 0.2V CS1 GND CS2 controlled VCC 3.0V CS2 tSDR Data Retention Mode tRDR VDR 0.4V GND CS20.2V 8 Revision 1.0 June 2002 K6F1008V2C Family PACKAGE DIMENSIONS 32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F) CMOS SRAM Units: millimeters(inches) 0.20 0.008 +0.10 -0.05 +0.004 -0.002 13.40 0.20 0.528 0.008 #32 #1 0.10 MAX 0.004 ( 8.40 0.331 MAX 8.00 0.315 0.25 ) 0.010 0.50 0.0197 #16 #17 1.00 0.10 0.039 0.004 0.25 0.010 TYP 11.80 0.10 0.465 0.004 +0.10 -0.05 0.006 +0.004 -0.002 0.15 0.05 0.002 MIN 1.20 0.047 MAX 0~8 0.45~0.75 0.018~0.030 ( 0.50 ) 0.020 9 Revision 1.0 June 2002 |
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